PDF Solutions Inc
PDFS Real Time Price USDRecent trades of PDFS by members of U.S. Congress
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Recently reported changes in PDFS holdings by institutional investors
Quarterly net insider trading by PDFS's directors and management
* Insider trading data parsed from SEC Form 4 filings by Quiver Quantitative. Sign up for the Quiver API for real-time access.
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About
Key Metrics
Return (1d)
Return (30d)
Return (1Y)
CAGR (Total)
Max Drawdown
Beta
Alpha
Sharpe Ratio
Win Rate
Average Win
Average Loss
Annual Volatility
Annual Std Dev
Information Ratio
Treynor Ratio
Total Trades
Metrics Definitions
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Alpha
Measures a portfolio's risk-adjusted performance against that of its benchmark
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Annual Standard Deviation
Measures how much the portfolio's total return varies from its mean or average.
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Annual Volatility
A statistical measure of the dispersion of returns for the portfolio.
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Average Win
The average return (%) for trades that resulted in a positive return.
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Average Loss
The average return (%) for trades that resulted in a negative return.
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Beta
A measure of the volatility of the portfolio compared to the market as a whole.
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CAGR
CAGR (Compounded Annual Growth Rate), is the historical annualized rate of return for an investment strategy, throughout the backtest period.
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Information Ratio
A measurement of portfolio returns beyond the returns of its benchmark compared to the volatility of those returns.
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Max Drawdown
the maximum observed loss from a peak to a trough of a portfolio, before a new peak is attained.
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Sharpe Ratio
The Sharpe Ratio is a measure of historical risk-adjusted return, which quantifies the amount of return that an investor received per unit of risk.
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Total Trades
The total number of trades made by this strategy.
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Treynor Ratio
Attempts to measure how successful an investment is in providing compensation to investors for taking on investment risk.
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Win Rate
The percentage of total trades that resulted in a positive return.
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Government lobbying spending instances
PDFS Estimated quarterly lobbying spending
PDFS Revenue by Segment or Geography
New PDFS patent grants
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Patent Title: Advanced node standard logic cells that utilizes ts cut mask(s) and avoid dfm problems caused by closely spaced gate contacts and tscut jogs May. 29, 2018
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Patent Title: Integrated circuit containing does of gatecnt-tip-to-side-short-configured, ncem-enabled fill cells May. 29, 2018
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Patent Title: Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from does of ncem-enabled fill cells on test wafers that include multiple means/steps for enabling nc detection of gatecnt-gate via opens Apr. 24, 2018
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Patent Title: Method for accurate measurement of leaky capacitors using charge based capacitance measurements Apr. 24, 2018
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Patent Title: Integrated circuit including ncem-enabled, side-to-side gap-configured fill cells, with ncem pads formed from at least three conductive stripes positioned between adjacent gates Apr. 17, 2018
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Patent Title: Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including tip-to-side short configured fill cells, and the second doe including chamfer short configured fill cells Mar. 27, 2018
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Patent Title: Process for making an integrated circuit that includes ncem-enabled, tip-to-side gap-configured fill cells, with ncem pads formed from at least three conductive stripes positioned between adjacent gates Mar. 27, 2018
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Patent Title: Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including side-to-side short configured fill cells, and the second doe including chamfer short configured fill cells Mar. 20, 2018
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Patent Title: Integrated circuit including ncem-enabled, snake-configured fill cells, with ncem pads formed from at least three conductive stripes positioned between adjacent gates Mar. 20, 2018
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Patent Title: Integrated circuit including ncem-enabled, via-open/resistance-configured fill cells, with ncem pads formed from at least three conductive stripes positioned between adjacent gate Mar. 06, 2018
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Patent Title: Integrated circuit including ncem-enabled, diagonal gap-configured fill cells, with ncem pads formed from at least three conductive stripes positioned between adjacent gates Mar. 06, 2018
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Patent Title: Integrated circuit including ncem-enabled, corner gap-configured fill cells, with ncem pads formed from at least three conductive stripes positioned between adjacent gates Mar. 06, 2018
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Patent Title: Process for making and using mesh-style ncem pads Mar. 06, 2018
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Patent Title: Integrated circuit containing standard logic cells and library-compatible, ncem-enabled fill cells, including at least via-open-configured, aacnt-short-configured, gatecnt-short-configured, and metal-short-configured, ncem-enabled fill cells Feb. 27, 2018
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Patent Title: Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from does of ncem-enabled fill cells on test wafers that include multiple means/steps for enabling nc detection of v0 via opens Feb. 27, 2018
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Patent Title: Process for making an integrated circuit that includes ncem-enabled, interlayer overlap-configured fill cells, with ncem pads formed from at least three conductive stripes positioned between adjacent gates Feb. 20, 2018
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Patent Title: Integrated circuit including ncem-enabled, tip-to-tip gap-configured fill cells, with ncem pads formed from at least three conductive stripes positioned between adjacent gates Jan. 30, 2018
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Patent Title: Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including tip-to-tip short configured fill cells, and the second doe including chamfer short configured fill cells Jan. 16, 2018
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Patent Title: Process for making semiconductor dies, chips and wafers using non-contact measurements obtained from does of ncem-enabled fill cells on test wafers that include multiple means/steps for enabling nc detection of aacnt-ts via opens Jan. 16, 2018
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Patent Title: Integrated circuit including ncem-enabled, interlayer overlap-configured fill cells, with ncem pads formed from at least three conductive stripes positioned between adjacent gates Jan. 16, 2018
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Patent Title: Snap-to valid pattern system and method Jan. 16, 2018
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Patent Title: Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including snake open configured fill cells, and the second doe including stitch open configured fill cells Jan. 09, 2018
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Patent Title: Method for manufacturing a semiconductor product wafer Dec. 19, 2017
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Patent Title: Integrated circuit containing does of gate-snake-open-configured, ncem-enabled fill cells Nov. 28, 2017
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Patent Title: Integrated circuit containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including tip-to-tip short configured fill cells, and the second doe including chamfer short configured fill cells Nov. 21, 2017
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Patent Title: Integrated circuit containing first and second does of standard cell compatible, ncem-enabled fill cells with first doe including tip-to-side short configured fill cells and second doe including chamfer short configured fill cells Nov. 14, 2017
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Patent Title: Integrated circuit containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including via open configured fill cells, and the second doe including metal island open configured fill cells Nov. 14, 2017
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Patent Title: Mesh-style ncem pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads Oct. 31, 2017
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Patent Title: Integrated circuit containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including chamfer short configured fill cells, and the second doe including corner short configured fill cells Oct. 24, 2017
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Patent Title: Integrated circuit containing does of ncem-enabled fill cells Oct. 24, 2017
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Patent Title: Integrated circuit containing standard logic cells and library-compatible, ncem-enabled fill cells, including at least via-open-configured, aacnt-short-configured, gate-short-configured, and ts-short-configured ncem-enabled fill cells Oct. 17, 2017
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Patent Title: E-beam inspection apparatus and method of using the same on various integrated circuit chips Oct. 17, 2017
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Patent Title: Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including snake open configured fill cells, and the second doe including metal island open configured fill cells Oct. 10, 2017
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Patent Title: Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including via open configured fill cells, and the second doe including stitch open configured fill cells Oct. 10, 2017
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Patent Title: Integrated circuit containing standard logic cells and library-compatible, ncem-enabled fill cells, including at least chamfer-short-configured, aacnt-short-configured, gatecnt-short-configured, and ts-short-configured, ncem-enabled fill cells Oct. 10, 2017
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Patent Title: Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from does of ncem-enabled fill cells on wafers that include multiple steps for enabling nc detecteion of aacnt-ts via opens Oct. 10, 2017
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Patent Title: Integrated circuit containing standard logic cells and library-compatible, ncem-enabled fill cells, including at least via-open-configured, ts-short-configured, metal-short configured, and aa-short-configured, ncem-enabled fill cells Oct. 03, 2017
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Patent Title: Integrated circuit containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including snake open configured fill cells, and the second doe including metal island open configured fill cells Oct. 03, 2017
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Patent Title: Integrated circuit containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including merged-via open configured fill cells, and the second doe including snake open configured fill cells Sep. 26, 2017
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Patent Title: Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including chamfer short configured fill cells, and the second doe including corner short configured fill cells Sep. 26, 2017
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Patent Title: Integrated circuit containing standard logic cells and library-compatible, ncem-enabled fill cells, including at least chamfer-short-configured, aacnt-short-configured, gate-short-configured, and gatecnt-short-configured, ncem-enabled fill cells Sep. 26, 2017
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Patent Title: Integrated circuit containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including side-to-side short configured fill cells, and the second doe including chamfer short configured fill cells Sep. 19, 2017
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Patent Title: Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including merged-via open configured fill cells, and the second doe including snake open configured fill cells Sep. 19, 2017
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Patent Title: Integrated circuit containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including merged-via open configured fill cells, and the second doe including metal island open configured fill cells Sep. 19, 2017
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Patent Title: Integrated circuit containing standard logic cells and library-compatible, ncem-enabled fill cells, including at least chamfer-short-configured, aacnt-short-configured, gate-short-configured, and ts-short-configured, ncem-enabled fill cells Sep. 12, 2017
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Patent Title: Integrated circuit containing standard logic cells and library-compatible, ncem-enabled fill cells, including at least via-open-configured, gatecnt-short-configured, metal-short-configured, and aa-short-configured, ncem-enabled fill cells Sep. 12, 2017
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Patent Title: Integrated circuit containing standard logic cells and library-compatible, ncem-enabled fill cells, including at least via-open-configured, aacnt-short-configured, gate-short-configured, and ts-short-configured, ncem-enabled fill cells Sep. 12, 2017
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Patent Title: Integrated circuit containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including via open configured fill cells, and the second doe including merged-via configured fill cells Sep. 12, 2017
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Patent Title: Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, ncem-enabled fill cells, with the first doe including side-to-side short configured fill cells, and the second doe including tip-to-side short configure Aug. 29, 2017
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Patent Title: Integrated circuit containing standard logic cells and library-compatible, ncem-enabled fill cells, including at least via-open-configured, aacnt-short-configured, gate-short-configured, and gatecnt-short-configured, ncem-enables fill cells Aug. 22, 2017
Federal grants, loans, and purchases
Estimated quarterly amount awarded to PDFS from public contracts
Recent insights relating to PDFS
Recent picks made for PDFS stock on CNBC
ETFs with the largest estimated holdings in PDFS
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- Is $PDFS stock a Buy, Sell, or Hold?
- What is the price target for $PDFS stock?
* Analyst consensus is not financial advice. Please see our data disclaimers .
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- Who owns $PDFS stock?
- Who owns the most shares of $PDFS stock?
- What funds own $PDFS stock?
* These are estimates based on data taken from SEC filings. There may be inaccuracies due to parsing errors, accidental double-counting, incorrect classification of indirectly owned shares, or any other number of issues.
The Quiver Smart Score combines our data on Congress Trading, Lobbying, Insider Trading, CNBC Mentions and more to provide a comprehensive view of the strength of a stock's underlying data.
The Smart Score grades stocks on a scale of 1 (weakest) to 10 (strongest) based on the strength of the underlying data.Sign Up to view PDFS Smart Score
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PDF Solutions Inc offers products and services designed to empower engineers and data scientists across the semiconductor ecosystem to improve the yield, quality, and profitability of their products. The solutions combine proprietary software, physical intellectual property (or IP) for integrated circuit (or IC) designs, electrical measurement hardware tools, various methodologies, and professional services. The company's products and services are sold to integrated device manufacturers (or IDMs), fabless semiconductor companies, foundries, outsourced semiconductor assembly and test (or OSATs), and system houses.
- Address Santa Clara, CA
- Market Cap 984.7 million
- Employees 539
- Industrial Classification Services-Prepackaged Software